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| IN74HCT163A PRESETTABLE COUNTERS High-Performance Silicon-Gate CMOS The IN74HCT163A is identical in pinout to the LS/ALS163. The IN74HCT163 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. The IN74HCT163A is programmable 4-bit synchronous counter that feature parallel Load, synchronous Reset, a Carry Output for cascading and count-enable controls. The IN74HCT163A is binary counter with synchronous Reset. * TTL/NMOS Compatible Input Levels * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 4.5 to 5.5 V * Low Input Current: 1.0 A LOGIC DIAGRAM ORDERING INFORMATION IN74HCT163AN Plastic IN74HCT163AD SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT PIN 16 =VCC PIN 8 = GND FUNCTION TABLE Rese t L H H H H X Load X L H H H X Inputs Enable Enable P T X X X X X L L X H H X X Clock Q0 L P0 Outputs Q1 Q2 L L P1 P2 No change No change Count up No change Q3 L P3 Function Reset to "0" Preset Data No count No count Count No count X=don't care P0,P1,P2,P3 = logic level of Data inputs Ripple Carry Out = Enable T * Q0 * Q1 * Q2 * Q3 1 IN74HCT163A MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin mA 20 IOUT DC Output Current, per Pin mA 25 ICC DC Supply Current, VCC and GND Pins mA 50 PD Power Dissipation in Still Air, Plastic DIP+ 750 mW SOIC Package+ 500 Tstg Storage Temperature -65 to +150 C 260 TL Lead Temperature, 1 mm from Case for 10 C Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types t r, tf Input Rise and Fall Time (Figure 1) Min 4.5 0 -55 0 Max 5.5 VCC +125 500 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 IN74HCT163A DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Guaranteed Limit VCC Symbol Parameter Test Conditions V 125 25 C 85 to C C -55C VOUT=0.1 V or VCC-0.1 V VIH Minimum High4.5 2.0 2.0 2.0 Level Input 5.5 2.0 2.0 2.0 IOUT 20 A Voltage VOUT=0.1 V or VCC-0.1 V VIL Maximum Low 4.5 0.8 0.8 0.8 Level Input 5.5 0.8 0.8 0.8 IOUT 20 A Voltage VIN=VIH or VIL VOH Minimum High4.5 4.4 4.4 4.4 Level Output 5.5 5.4 5.4 5.4 IOUT 20 A Voltage VIN=VIH or VIL 4.5 3.98 3.84 3.7 IOUT 6.0 mA VIN=VIH or VIL VOL Maximum Low4.5 0.1 0.1 0.1 Level Output 5.5 0.1 0.1 0.1 IOUT 20 A Voltage VIN=VIH or VIL 4.5 0.26 0.33 0.4 IOUT 6.0 mA IIN Maximum Input VIN=VCC or GND 5.5 0.1 1.0 1.0 Leakage Current VIN=VCC or GND ICC Maximum 5.5 4.0 40 160 Quiescent Supply IOUT=0A Current (per Package) VIN = 2.4 V, Any One Additional 25C to ICC Quiescent Supply Input 55C 125C VIN=VCC or GND, Current Other Inputs 5.5 2.9 2.4 IOUT=0A Unit V V V V A A mA 3 IN74HCT163A AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V 10%, CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit Unit Symbol Parameter 25 C to 85 125 -55C C C fmax Maximum Clock Frequency (Figures 1,6) 30 24 20 MHz tPLH Maximum Propagation Delay, Clock to Q 34 43 51 ns tPHL (Figures 1,6) 41 51 62 ns tPLH Maximum Propagation Delay, Enable T 32 40 48 ns to Ripple Carry Out (Figures 2,6) tPHL 39 49 59 ns tPLH Maximum Propagation Delay, Clock to 35 44 53 ns Ripple tPHL Carry Out (Figures 1,6) 43 54 65 ns tTLH, tTHL Maximum Output Transition Time, Any 15 19 22 ns Output, (Figures 1 and 6) CIN Maximum Input Capacitance 10 10 10 pF Power Dissipation Capacitance (Per Typical @25C,VCC=5.0 V Gate) 60 pF CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC+ICCVCC TIMING REQUIREMENTS (VCC=5.0 V 10%, CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit Symbol Parameter Unit 25 C to 85 125 -55C C C tsu Minimum Setup Time, Preset Data Inputs to 30 38 45 ns Clock (Figure 4) tsu Minimum Setup Time, Load to Clock (Figure 27 34 41 ns 4) tsu Minimum Setup Time, Reset to Clock 32 40 48 ns (Figure 3) tsu Minimum Setup Time, Enable T or Enable P 40 50 60 ns to Clock (Figure 5) th Minimum Hold Time, Clock to Preset Data 10 13 15 ns Inputs (Figure 4) th Minimum Hold Time, Clock to Load (Figure 3 3 3 ns 4) th Minimum Hold Time, Clock to Reset (Figure 3 3 3 ns 3) th Minimum Hold Time, Clock to Enable T or 3 3 3 ns Enable P (Figure 5) trec Minimum Recovery Time, Load Inactive to 25 31 38 ns Clock (Figure 4) tw Minimum Pulse Width, Clock (Figure 1) 16 20 24 ns tw Minimum Pulse Width, Reset (Figure 4) 16 20 24 ns tr, tf Maximum Input Rise and Fall Times (Figure 500 500 500 ns 1) 4 IN74HCT163A Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms Figure 5. Switching Waveforms Figure 6. Test Circuit 5 IN74HCT163A VCC=Pin 16 GND=Pin 8 The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A Toggle-Enable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip-flop low. Figure 7.Expanded logic diagram 6 IN74HCT163A 1. 2. 3. 4. Sequence illustrated in waveforms: Reset outputs to zero. Preset to binary twelve. Count to thirteen, fourteen, fifteen, zero, one, and two. Inhibit. Figure 8. Timing Diagram 7 IN74HCT163A TYPICAL APPLICATIONS CASCADING Note:When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend on number of stages. This limitation is due to set up times between Enable (Port) and clock. Figure 9. N-Bit Synchronous Counters Figure 10. Nibble Ripple Counter 8 |
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